The present invention relates to a sampling frequency conversion circuit which converts an input digital signal series with the first sampling frequency M (samples/period(T)) and n quantization bits, to an output digital signal series with N (samples/period(T)) and n' quantization bits, where N is an interger different from the interger M. The present invention relates in particular to such a circuit which converts with high conversion speed, and requests small capacity of memory for conversion calculation.
First, a prior conversion process is described. When an input signal series with M (samples/period(T)) is converted to an output signal series with N samples/period(T), an intermediate signal series with L samples/period(T) is provided, where L is the common multiple of the integers M and N, and then, an output sampling signal is derived from said intermediate signal with L samples/period(T) for every predetermined duration. That process is described in detail in accordance with FIG. 1, where it is supposed that an input signal frequency is 5 samples/period, and an output signal frequency is 6 samples/period, and each sample has n=9 quantization bits.
FIG. 1(a) shows an input signal series which has 5 samples (T.sub.n-5 - - - T.sub.n-1, T.sub.n-4 - - - T.sub.0, et al.) in a period (T), and FIG. 1(d) shows an output signal series which has 6 samples (W.sub.n-6 - - - W.sub.n-1, W.sub.n-5 - - - W.sub.0, et al.) in said period (T). In order to obtain the output signal series of FIG. 1(d), the signal series of FIG. 1(b) which has the input signal series of FIG. 1(a) and five ((30/5)-1=5) samples with amplitude zero inserted between each input samples, is obtained. Then, the intermediate signal series of FIG. 1(b) is processed by a low-pass filter with the bandwidth .pi./(number of inserted zeros, plus one)=.pi./6 so that said zero samples in FIG. 1(b) are converted to interpolated samples between each input samples. The signal of FIG. 1(c) is the output of said process of interpolation. The signal series of FIG. 1(c) has 30 samples/period(T). The output signal series of FIG. 1(d) is obtained by extracting a pulse in FIG. 1(c) for every 5 (=30/6) pulses. Thus, the signal of FIG. 1(d) has 6 samples/period(T).
Said interpolation process, or a low-pass filtering process is accomplished by using a finite impulse response filter (FIR), or a transversal filter, which satisfies a linear phase condition.
FIG. 2 is a block diagram of a conventional transversal filter, in which the reference numeral 1 is an input terminal, 2 is an output terminal, 3 is a shift register with delay elements 3.sub.1 through 3.sub.61 each holding one sample value, 4.sub.1 through 4.sub.61 are multiplicators with multipliers h.sub.-30 through h.sub.30, respectively, and 5 is an adder for providing the sum of the outputs of the multiplicators 4.sub.1 through 4.sub.61. The transversal filter of FIG. 2 has 61 taps, which may be, however, another value, since the number of taps is selected according to the desired accuracy or error of an output signal. When an input signal of FIG. 1(b) is applied to the input terminal 1 of FIG. 2, an output signal of FIG. 1(c) is obtained at the output terminal 2 of FIG. 2.
In FIG. 2, the following equation (1) is satisfied where x.sub.k is the value of each of the input samples, z.sub.k is the value of each of the output samples, and h.sub.m is a multiplier of each of the multiplicators. ##EQU1## As apparent from the equation (1), the calculation of 61 multiplications and 60 additions is necessary for obtaining each single output sample W.sub.k. That amount of calculation is extravagant, and therefore, the transversal filter of FIG. 2 is not suitable in the field which requests high speed interpolation calculation, like the field of a picture information processing.
In order to solve the above problem, the following solution may be possible. It should be noted in FIG. 1 that no calculation is necessary for an output sample which is not extracted, and for input sample with the value zero. For instance, the output sample W.sub.n in FIG. 1(d) is obtained only with 11 input samples x.sub.-5 through x.sub.5, and 11 multipliers (h.sub.0, h.sub..+-.6, h.sub..+-.12, h.sub..+-.18, h.sub..+-.24, and h.sub..+-.30). The output sample W.sub.n is, in fact, the same as the input sample x.sub.n, and therefore, no calculation is necessary for obtaining the output sample W.sub.n. However, for the sake of the simplicity of the explanation, the calculation for obtaining the output sample W.sub.n is supposed to be accomplished in the above explanation. FIG. 1(e) shows the necessary multipliers for obtaining the output samples W.sub.n through W.sub.n+ 6, and the following table 1 shows the same information.
TABLE 1 ______________________________________ Coefficient h.sub.m Number Sub-filter (value of m is shown) of taps ______________________________________ 1 -30, -24, -18, -12, -6, 0, 6, 12, 18, 24, 30 11 2 -29, -23, -17, -11, -5, 1, 7, 13, 19, 25, 10 3 -28, -22, -16, -10, -4, 2, 8, 14, 20, 26 10 4 -27, -21, -15, -9, -3, 3, 9, 15, 21, 27 10 5 -26, -20, -14, -8, -2, 4, 10, 16, 22, 28 10 6 -25, -19, -13, -7, -1, 5, 11, 17, 23, 29 10 ______________________________________
It should be appreciated in FIG. 1(e) and the table 1 that the multiplier of the interpolation filter has the period of 6 samples. Due to the presence of the periodicity, 6 (=L/M=30/5=K.sub.m) sub-filters which have only 10 or 11 taps and are used recursively, may replace the interpolation filter of FIG. 2 which has 61 taps, for providing an output signal with N samples/period(T) from an input signal series with M samples/ period(T).
FIG. 3 is another prior art which considers the above analysis. In FIG. 3, the shift register 3 has 11 taps, and the coefficient or the tap coefficient 6.sub.1 through 6.sub.11 of the multiplicators 6.sub.1 through 6.sub.11 is variable. Each time a signal of FIG. 1(a) is applied to the input terminal 1, a set of coefficients for the designated sub-filter as shown in the table 1 are provided to the multiplicators 6.sub.1 through 6.sub.11. And, said set of coefficients of the multiplicators 6.sub.1 through 6.sub.11 are selected recursively for each input signal. Then, an output signal is provided at the output terminal 6. In case of FIG. 3, since the speed of the output signal series is the same as that of the input signal series, the output signal is temporarily stored in a memory, which is read out with the desired speed (6 samples/period(T) in this case).
However, the embodiment of FIG. 3 still has the disadvantage that the operating speed is not fast enough, since the amount of calculation is 11 multiplications and 10 additions.
In order to solve the above problems a ROM which stores the result of the calculation has been used. The filter process in a sub-filter which is composed according to FIG. 1 and the table 1 is similar to the equation (1), and is shown below. ##EQU2## Said equation (2) is changed to the equation (4) when a sampled value x.sub.k is a binary value as shown in the equation (3); ##EQU3## Accordingly, the ROM stores the value ##EQU4## at the address (a.sub.i.sup.(k-m) ; 1.ltoreq.m.ltoreq.11), and the output of said ROM is applied to the shift register which performs the multiplication with 2.sup.i and the addition. Said addition is performed (n-1) times, that is to say, when n=9 that addition is performed 8 times.
By the way, the necessary capacity of that ROM (read only memory) is shown by the equation (5); EQU 2.sup.(number of taps of a sub-filter) .times.C.times.n (5)
where C is a number of bits for expressing the coefficients of a filter. When C=9, the capacity of a ROM is (2.sup.11 .times.9.times.9) bits for each sub-filter. Since 6 sub-filters are used, the total capacity of the ROM is about 2.sup.20 bits. And, the number of the necessary process is (n-1)=8 times, in which each process includes the reading out the ROM and the addition. Said number (=8) may be reduced to n=4, if a parallel calculation is accomplished. If we desire to perform the high speed calculation, a simultaneous calculation which performs the calculation for a plurality of bit planes simultaneously must be performed. For instance, when the number of taps is 11, n=9 and C=9, then, the number of the necessary addresses of the ROM is 2.sup.99 which relates to the total number of bits (=99(11.times.9)), and the number of the total bits of the ROM is even 9.times.2.sup.99.
It should be appreciated that said number 9.times.2.sup.99 is extravagant. Therefore, an improved calculation which is high in speed, and uses less capacity of memory has been desired.